Computing systems having multiple bus masters are well known. Indeed, microprocessor designs typically allow a bus to have multiple masters through a defined bus arbitration scheme. Typically, an external device requests “ownership” of a bus via a bus request signal. This signal is directed to an arbitration device that grants ownership of the bus through a bus grant signal. Typically, devices capable of operating as a master of a given bus have logic for generating a bus request signal, as well as logic for receiving a bus grant signal. In turn, the bus request signals are directed to arbitration logic, which arbitration logic also generates the bus grant signals that are delivered to the various bus masters. The bus arbitration logic coordinates and manages the bus mastership, assigning mastership to only one master at a time, in order to avoid bus contentions.
In most systems, a given bus master is unaware of the activities of other bus masters. In this regard, a given bus master may request mastership of a bus, but then await the grant of the bus mastership by the arbitration logic. Further, a given bus master typically has no antecedent knowledge as to how long it will wait to receive the grant of its bus request.
Typically, functional logic that is contained within the various bus masters remains fully operational at all times (albeit inactive at times). When maintained at an operational state, power is constantly consumed by the various logic components within the functional logic. Since a given bus master may wait for an extended period of time between requesting mastership of a bus and the grant of that mastership, excess power is often consumed by the quiescent operation of functional and other logic components within the bus master.
Accordingly, it is desired to provide a novel system and method for reducing excess power consumption in a bus master of a multi-master computer system.